The present invention relates to a nonvolatile memory device and a process for fabricating the same and, more particularly, to a technology which is effective if applied to a nonvolatile memory device such as the so-called "flash ROM (Read Only Memory)" capable of having electrically writing and erasing operations and a fabricating process of the same.
A program memory in a microcomputer is divided into the ROM (Read Only Memory) in which data are written in its fabrication process, the EPROM (Erasable & Programmable Read Only Memory) in which data are electrically written after the fabrication and erased with the irradiation of ultraviolet rays, and the EEPROM (Electrically Erasable & Programmable Read Only Memory) in which the erasing operation is also electrically carried out. For easy program debugging, the EPROM or EEPROM is widely used.
The flash ROM or a kind of EEPROM is disclosed in U.S. Pat. No. 4,949,309, for example. Here is disclosed a memory array of the so-called "NOR type", in which each of memory cells is comprised of a single MISFET and in which the memory cells are arranged at the intersections of word lines and data lines. Moreover, the write/erase of this kind of flash memory is disclosed on pp. 111 to 114 of 1990 IEDM (International Electron Devices Meeting) Tech. Dig., 1990.
In order to reduce the size of the memory array, on the other hand, there has been developed the so-called "contactless array" in which the proprietary source lines and data lines are not provided unlike the NOR type but in which common source lines and data lines are formed of buried semiconductor regions so that they may be shared between adjacent memory cells. The nonvolatile memory device having such contact array is disclosed, for example, on pp. 311 to 314 of 1991 IEDM (International Electron Devices Meeting) Tech. Dig., 1991 (as will be called as the first reference of the prior art).
In U.S. Pat. No. 4,887,238 (as will be called the second reference of the prior art), there is disclosed the EPROM which is given the split gate structure by interposing both MOSFETs (Metal-Oxide-Semiconductor FETs) comprised of control gates and nonvolatile memory elements comprised of floating gates and control gates between data lines formed of a buried layer.
On pp. 432 to 435 of IEEE, IEDM 88, 1988 (as will be called the third reference of the prior art), there is disclosed an EPROM which is made asymmetric by forming an N.sup.- -type layer in one of data lines of a buried N.sup.+ -type layer so that the writing operation and the erasing operation may be carried out in opposite biases.